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NXP Semiconductors /LPC176x5x /SYSCON /PLL1CON

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Interpret as PLL1CON

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PLLE1)PLLE1 0 (PLLC1)PLLC1 0RESERVED

Description

PLL1 Control Register

Fields

PLLE1

PLL1 Enable. When one, and after a valid PLL1 feed, this bit will activate PLL1 and allow it to lock to the requested frequency.
PLLC1

PLL1 Connect. Setting PLLC to one after PLL1 has been enabled and locked, then followed by a valid PLL1 feed sequence causes PLL1 to become the clock source for the USB subsystem via the USB clock divider. See PLL1STAT register.
RESERVED

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data